Back-to-back power loss protection
US11954334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to increasing data storage device lifetime by detecting synthetic PLP tests. Both upper and lower PLP time thresholds are set. When the PLP time is above the upper threshold, the data storage device is in a defensive PLP idle state. When the PLP time is between the upper and lower thresholds, the data storage device is in a defensive PLP detecting state. When the PLP time is below the lower threshold, the data storage device may enter the defensive PLP state if the number of times the PLP time is below the lower PLP time threshold either a consecutive number of times or a set number of times within a predefined window of time. While in the defensive PLP state, mounting is not completed and hence, a host device will not send any I/O commands and thus, not waste a PEC count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.