Zero latency digital assistant
US11954405B2 · kind B2 · utility
1Cited by
817References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Nov 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M2250/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device can implement a zero-latency digital assistant by capturing audio input from a microphone and using a first processor to write audio data representing the captured audio input to a memory buffer. In response to detecting a user input while capturing the audio input, the device can determine whether the user input meets a predetermined criteria. If the user input meets the criteria, the device can use a second processor to identify and execute a task based on at least a portion of the contents of the memory buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.