Semiconductor memory device and memory system including the same
US11955159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.