Computing-in-memory accelerator design with dynamic analog RAM cell and associated low power techniques with sparsity management
US11955167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Mar 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1; a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.