Semiconductor storage device and erase verification method
US11955188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Nov 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device of an embodiment includes a memory block, a resistance measurement circuit, and a control circuit. The memory block includes first to third control signal lines connected to gates of a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor. The resistance measurement circuit measures resistance of at least one control signal line among the first to third control signal lines. The control circuit performs erase, program, and read of data at the plurality of memory cell transistors included in the memory block. The control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.