Memory device and method for shifting memory values
US11955197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Oct 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S−1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.