Semiconductor-controlled rectifier with low trigger voltage for electrostatic discharge protection

US11955472B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Meng Miao · Williston, US
• Alain Loiseau · Williston, US
• Souvick Mitra · South Burlington, US
• Wei Liang · South Burlington, US
• Robert J. Gauthier, JR. · Williston, US
• Anindya Nath · Butlers Corners, US

Key dates

• Filing date: Dec 17, 2021
• Grant date: Apr 9, 2024
• Expiry date: May 9, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/713

Abstract

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.