Display device including multi-layered buffer layer
US11956998B2 · kind B2 · utility
0Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Jan 4, 2023 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jan 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/8731
Abstract
A display device includes: a first substrate including a pixel area and a transmissive area; a thin-film transistor on the first substrate; a planarization layer on the thin-film transistor; a first light emitting electrode on the planarization layer; a bank covering a part of the first light emitting electrode; a light emitting layer on the first light emitting electrode; and a second light emitting electrode on the light emitting layer and the bank. The transmissive area includes a transmissive hole penetrating the bank and the planarization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.