Configurable routing in a multi-chip system
US11960392B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Oct 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.