Operation accelerator and compression method
US11960421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jul 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.