Method and system for managing memory associated with a peripheral component interconnect express (PCIE) solid-state drive (SSD)
US11960723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Oct 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing a memory associated with PCIe SSD including: generating memory pools of equal size from a predefined size of contiguous physical memory, each of the memory pools manages a memory request of different size and is associated with a respective predefined size of memory request; dividing each of the memory pools into first set of memory pages, each having a size equal to maximum size among the predefined size of the memory request associated with the respective memory pool; dividing each of the first set of memory pages into second set of memory pages, each having a size equal to the predefined size of the memory request associated with respective memory pool; and managing the contiguous physical memory by allocating a memory page from the second set of memory pages fora memory request corresponding to the size of the second set of memory pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.