Manufacture method of array substrate, array substrate, and display panel
US11961852B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 13, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 Å to 6000 Å; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.