Synchronization between data and clock signals in high-speed interfaces
US11962310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Sep 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.