Integrated circuit read only memory (ROM) structure
US11963348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.