Neural processor
US11966358B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2023 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Aug 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device comprises a first set of processors comprising a first processor and a second processor, each of which comprises at least one controllable port, a first memory operably coupled to the first set of processors, at least one forward data line configured for one-way transmission of data in a forward direction between the first set of processors, and at least one backward data line configured for one-way transmission of data in a backward direction between the first set of processors. wherein the first set of processors are operably coupled in series via the at least one forward data line and the at least one backward data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.