Interrupt latency and interval tracking
US11966471B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jul 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Secure circuitry detects a latency between when an interrupt occurred and when the interrupt was released in correspondence with handling of the interrupt. The secure circuitry detects an interval between consecutive occurrences of the interrupt. In response to either or both of the latency exceeding a latency limit and the interval exceeding an interval limit, the secure circuitry performs an action.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.