Method and system for comprehensively evaluating reliability of multi-chip parallel IGBT module
US11966683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Sep 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module are provided. The method includes: establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, performing a chip fatigue failure test, and selecting a gate-emitter voltage as a failure characteristic quantity; establishing a transconductance reliability model of the multi-chip parallel IGBT module, performing a bonding wire shedding failure test, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; using a Pearson correlation coefficient to characterize a degree of health of the IGBT module, and respectively calculating degrees of health PPMCCC and PPMCCB in different degrees of chip fatigue and bonding wire shedding failure states; and comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCCC and PPMCCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.