Interconnect device for selectively accumulating read data and aggregating processing results transferred between a processor core and memory
US11966736B2 · kind B2 · utility
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5References
26Claims
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Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Sep 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation of sets of data stored in a memory and an aggregation of results processed by the processing core; and provide a result of the performing of the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.