Write signal interference cancellation across data/servo clock boundary
US11967341B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2023 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/59688
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.