Memory unit with time domain edge delay accumulation for computing-in-memory applications and computing method thereof
US11967357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Sep 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.