Reconfigurable compute memory
US11967366B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.