Method for making high-voltage thick gate oxide
US11967520B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.