Laterally-gated transistors and lateral Schottky diodes with integrated lateral field plate structures

US11967619B2 · kind B2 · utility

Assignee

• TELEDYNE SCIENTIFIC & IMAGING, LLC · US

Inventors

• Keisuke Shinohara · Thousand Oaks, US
• Casey King · Austin, US
• Eric Regan · Moorpark, US
• Miguel Urteaga · Moorpark, US

Key dates

• Filing date: Sep 16, 2020
• Grant date: Apr 23, 2024
• Expiry date: Jan 10, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.