Semiconductor structure, high electron mobility transistor and fabrication method thereof
US11967642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Nov 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/602
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.