Modularized power amplifier devices and architectures
US11967937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2019 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Aug 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor chip includes a semiconductor sub strate having formed thereon: radio-frequency (RF) input and output contact pads, DC contact pads, and first and second amplifier stages. An input of the first amplifier stage is coupled with the RF input contact pad. An input and an output of the second amplifier stage are respectively coupled to an output of the first amplifier stage and the RF output contact pad. The DC contact pads and the input of the first amplifier stages are connected via an input bias coupling path. The outputs of the amplifier stages are connected via an output bias coupling path. The chip further includes a lead frame having RF input and output pins electrically coupled to the RF input and output contact pads, and input bias pins electrically coupled to the DC contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.