Oscillation system including frequency-locked loop logic circuit and operating method thereof
US11967962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.