High performance feedback loop with delay compensation
US11967963B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/37
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.