Clock synchronization in a network using a distributed pulse signal
US11967964B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Mar 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.