Circuit compiling device and circuit evaluation device
US11968290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2019 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Apr 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments are directed to a circuit compiling device for compiling a function into a binary circuit and a function evaluation device for evaluating a function using such a binary circuit. The binary circuit comprises conjunction subcircuits each computing a conjunction of function input bits and XOR subcircuits each computing a function output bit. Each function output bit may be represented as a sum of interpolation terms, the plurality of function input bits and the interpolation terms of the one or more function output bits together forming a plurality of interpolation terms. A conjunction subcircuit computes an interpolation term as a conjunction of two interpolation terms. A XOR subcircuit computes a function output bit as a XOR of interpolation terms. Thereby, the first interpolation term and second interpolation term are also used in XOR subcircuits, hence the binary circuit has a smaller number or likelihood of ineffective faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.