Semiconductor memory devices
US11968824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2023 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Apr 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.