Aging mitigation
US11971741B2 · kind B2 · utility
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15References
42Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 6, 2021 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.