Patent · US Active

Computing system with write-back and invalidation in a hierarchical cache structure based on at least one designated key identification code

US11971821B2 · kind B2 · utility

1Cited by

1References

36Claims

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Assignee

SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD. · CN

Inventors

Weilin Wang · Zhejiang, CN
Yingbing Guan · Shanghai, CN
Lei Yi · Xi'an, CN

Key dates

Filing date	Oct 14, 2022
Grant date	Apr 30, 2024
Priority date	—
Expiry date	Oct 14, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0891
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computing system with a first instruction of an instruction set architecture (ISA) for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for write-back and invalidation in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one write-back and invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each write-back and invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.