Processor interface assembly, operation method, and processor
US11971837B2 · kind B2 · utility
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4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Feb 21, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor interface assembly includes: a first interface circuit including a plurality of sub-interface circuits and configured to couple with a plurality of peripheral devices, wherein the plurality of peripheral devices is configured to occupy a pre-determined address space, and the pre-determined address space includes multiple sub-address spaces; and a controller including a register and configured to set a sub-address space occupied by at least one type of peripheral devices among the plurality of peripheral devices based on at least a portion of data stored in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.