Method and system for overlapping sliding window segmentation of image based on FPGA
US11972504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2023 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | May 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed a method and a system for overlapping sliding window segmentation of an image based on an FPGA. According to the method, on-chip BRAMs storage resource cost of FPGA is determined; each on-chip BRAM in FPGA is used to cache the pixel data of each segmented sub-image in parallel; when the pixel data received by the BRAMs reaches a preset threshold or the last pixel of the segmented sub-image is written into the on-chip BRAMs, the data is written from the on-chip BRAMs to an off-chip DDR memory in a burst continuous writing mode; the repeated data generated by segmentation of horizontally overlapping sliding windows are written into the on-chip BRAMs corresponding to the current segmented sub-image and adjacent segmented sub-images thereof respectively in a synchronous and parallel manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.