Device for suppressing potential induced degradation and system
US11973349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Jul 13, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/56
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Provided are a device for suppressing potential induced degradation and a system. The device includes a rectification circuit, a non-isolated voltage conversion circuit and at least one capacitor. An input terminal of the rectification circuit is connected to an output terminal of a converter, the rectification circuit is configured to rectify an alternating current outputted by the converter into a direct current, the non-isolated voltage conversion circuit is configured to perform voltage conversion on the direct current outputted by the rectification circuit, and the voltage conversion is boost conversion or voltage reverse conversion. The capacitor is connected in parallel with an output terminal of the direct current, and either a positive electrode or a negative electrode of the capacitor is grounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.