Latch circuit and equalizer including the same
US11973623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Jun 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03445
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.