IQ clock phase calibration
US11973625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Mar 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communication circuit is disclosed. The communication circuit includes a calibration system, configured to receive clock signals respectively having first and second clock phases, and first and second duty cycles, where the calibration system is further configured to receive input data and to adjust the input data to generate adjusted data based partly on the input data and based partly on the first and second duty cycles. The communication circuit also includes a mixer, configured to receive the clock signals and to receive the adjusted data, where the mixer is configured to generate output data based on the clock signals and the adjusted data, and where a mismatch in the output data caused by the first and second duty cycles being different is reduced because of the adjustment made to the input data to generate the adjusted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.