Composing diverse remote cores and FPGAs
US11973697B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.