Semiconductor device including data storage pattern
US11974437B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Jul 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/697
Abstract
A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.