Low-area, low-power neural recording circuit, and method of training the same
US11974848B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 2, 2019 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jun 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/165
- WIPO fieldMedical technology
- WIPO sectorInstruments
Abstract
A sensor circuit that is capable of sensing of neural action potentials is disclosed. The circuit can be designed to minimize power dissipation and total silicon area so that it can be incorporated into a massively parallel sensor array and ultimately implanted in the body (e.g. into the brain) in a safe manner. The circuit can also be designed to be tunable such that it can be optimized in silico prior to fabrication, and can be optimized through the use of controllable current sources after fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.