Glitch-free synchronization and SYSREF windowing and generation scheme
US11977407B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 28, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Feb 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.