Pixel array substrate
US11978417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2023 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jun 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel array substrate includes multiple data lines, multiple scan lines and multiple pixel structures. The scan lines include an m-th scan line and an (m+1)-th scan line arranged in sequence, and m is a positive integer. The pixel structures include first to twenty-fourth pixel structures. A control terminal of a transistor of the seventh pixel structure and a control terminal of a transistor of the eighth pixel structure are electrically connected to the (m+1)-th scan line and the m-th scan line respectively. A control terminal of a transistor of the thirteenth pixel structure and a control terminal of a transistor of the fourteenth pixel structure are electrically connected to the (m+1)-th scan line and the m-th scan line respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.