Back pattern counter measure for solid state drives
US11978490B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | May 24, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Sep 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure includes back pattern counter measures for solid state drives. Embodiments described herein include setting and applying read threshold offsets according to flags set based on an amount of data stored within a memory block (e.g., an “openness” of the block). The flag is implemented during read commands to account for shifts in voltage distribution of open blocks. A value of the flag may be chosen based on a number of word lines included in the block that store data. The read threshold offsets may further be based on at least one of the set flag or an age of a respective NAND cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.