Method and apparatus for testing adjustment circuit
US11978498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.