Semiconductor memory device and method
US11978501B2 · kind B2 · utility
0Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.