Input signal shaping for a programmable logic array
US11979153B2 · kind B2 · utility
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26References
19Claims
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Key dates
| Filing date | Apr 29, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Apr 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.