Oversampled phase lock loop in a read channel
US11979163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Oct 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0998
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.