Method and wire-line transceiver for performing serial loop back test
US11979263B2 · kind B2 · utility
0Cited by
30References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jul 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03031
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.