Detecting anomalous latent communications in an integrated circuit chip
US11983087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2020 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Jan 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip. The method includes: (i) monitoring communications between a first component of the IC chip and other components of the IC chip, each communication comprising a command sent from the first component to another component, and a response received by the first component from that other component, the monitoring comprising: measuring the number of communications in each of a series of monitored time windows, and measuring the latency of each communication in the series of monitored time windows; (ii) calculating a maximum tolerable latency for each operational time window of the first component from the number of communications in that operational time window, an available stall time of the first component in that operational time window, and a latency penalty factor for that operational time window; and (iii) determining a measured latency to be anomalous if the measured latency is greater than the maximum tolerable latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.