System, device and method for accessing device-attached memory
US11983115B2 · kind B2 · utility
0Cited by
5References
23Claims
0Family size
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Key dates
| Filing date | Feb 8, 2023 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Feb 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.